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_______________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, pl ease contact maxim direct at 1-888-629-4642, or visit maxim?s website at www.maxim-ic.com. gigabit multimedia serial link deserializer with lvds system interface max9268 general description the max9268 deserializer utilizes maxim?s gigabit multimedia serial link (gmsl) technology. the max92 68 deserializer features an lvds system interface for reduced pin count and a smaller package, and pairs with any gmsl serializer to form a complete digital serial link f or joint transmission of high-speed video, audio, and bidire ctional control data. the max9268 allows a maximum serial payload data rate of 2.5gbps for a 15m shielded twisted-pair (st p) cable. the deserializer operates up to a maximum output clock rate of 104mhz (3-channel lvds) or 78m hz (4-channel lvds). this serial link supports display panels from qvga (320 x 240) to wxga (1280 x 800) a nd higher with 24-bit color. the 3-channel mode outputs an lvds clock, three lan es of lvds data (21 bits), uart control signals, and o ne i 2 s audio channel consisting of three signals. the 4-ch annel mode outputs an lvds clock, four lanes of lvds data (28 bits), uart control signals, an i 2 s audio channel, and auxiliary control outputs. the three audio outp uts form a standard i 2 s interface, supporting sample rates from 8khz to 192khz and audio word lengths of 4 to 32 bits. the embedded control channel forms a full-dup lex, differential, 100kbps to 1mbps uart link between th e serializer and deserializer. an electronic control unit (ecu), or microcontroller ( f c), can be located on the serializer side of the link (typical for video display), on th e max9268 side of the link (typical for image sensing), or on both sides. in addition, the control channel enables ecu/ f c control of peripherals on the remote side, such as backlight c ontrol, grayscale gamma correction, camera module, and touc h screen. base-mode communication with peripherals us es either i 2 c or the gmsl uart format. in addition, the max9268 features a bypass mode that enables full-duplex communication using custom uart formats. the gmsl serializer driver preemphasis, along with the max9268 channel equalizer, extends the link length and enhances the link reliability. spread spectrum is a vailable to reduce emi on the lvds and control outputs of th e max9268. the serial line inputs comply with iso 106 05 and iec 61000-4-2 esd protection standards. the core supply for the max9268 is 3.3v. the i/o su pply ranges from 1.8v to 3.3v. the max9268 is available in a 48-pin tqfp package (7mm x 7mm) with an exposed pad, and is specified over the -40 n c to +105 n c automotive temperature range. features s pairs with any gmsl serializer s 2.5gbps payload-rate ac-coupled serial link s scrambled 8b/10b line coding s supports wxga (1280 x 800) with 24-bit color s 8.33mhz to 104mhz (3-channel lvds) or 6.25mhz to 78mhz (4-channel lvds) output clock s 4-bit to 32-bit word length, 8khz to 192khz i 2 s audio channel supports high-definition audio s embedded half-/full-duplex bidirectional control channel (100kbps to 1mbps) s two 3-level inputs support 9 device addresses s interrupt supports touch-screen functions for display panels s i 2 c master for peripherals s equalizer for serial link input s programmable spread spectrum on the lvds and control outputs for reduced emi s serial-data clock recovery eliminates an external clock s automatic data-rate detection allows on-the-fly data-rate change s built-in prbs generator for ber testing of the serial link s iso 10605 and iec 61000-4-2 esd protection s -40 n c to +105 n c operating temperature range s 1.8v to 3.3v i/o and 3.3v core supplies s patent pending 19-5211; rev 2; 1/11 ordering information applications high-resolution automotive navigation rear-seat infotainment megapixel camera systems /v denotes an automotive qualified product. + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. t = tape and reel. evaluation kit available part temp range pin-package max9268gcm/v+ -40 n c to +105 n c 48 tqfp-ep* max9268gcm/v+t -40 n c to +105 n c 48 tqfp-ep* downloaded from: http:///
gigabit multimedia serial link deserializer with lvds system interface max9268 2 ______________________________________________________________________________________ absolute maximum ratings package thermal characteristics (note 1) 48 tqfp junction-to-ambient thermal resistance ( b ja ) .......27.6c/w junction-to-case thermal resistance ( b jc ).................2c/w note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. avdd to agnd ....................................................-0.5v to +3.9v dvdd, iovdd to agnd .......................................-0.5v to +3.9v gnd to agnd ......................................................-0.5v to +0.5v in+, in- to agnd .................................................-0.5v to +1.9v txout__, txclkout_ to agnd ........................-0.5v to +3.9v all other pins to gnd ......................... -0.5v to (v iovdd + 0.5v) txout__, txclkout_ short circuit to ground or supply ...............................................................continuous continuous power dissipation (t a = +70c) 48-pin tqfp (derate 36.2mw/c above +70c) ....2898.6mw human body model (r d = 1.5k, c s = 100pf) (in+, in-) to agnd ..........................................................8kv (txout__, txclkout_) to agnd .................................8kv all other pins to gnd ...................................................3.5kv iec 61000-4-2 (r d = 330, c s = 150pf) contact discharge (in+, in-) to agnd ..................................................10kv (txout__, txclkout_) to agnd ............................8kv air discharge (in+, in-) to agnd ........................................................12kv (txout__, txclkout_) to agnd ...............................20kv iso 10605 (r d = 2k, c s = 330pf) contact discharge (in+, in-) to agnd ..........................................................8kv (txout__, txclkout_) to agnd .................................8kv air discharge (in+, in-) to agnd ........................................................15kv (txout__, txclkout_) to agnd ...............................30kv operating temperature range ........................ -40c to +105c junction temperature .....................................................+150c storage temperature range ............................ -65c to +150c lead temperature (soldering, 10s) ................................+300c soldering temperature (reflow) ......................................+260c stresses beyond those listed under ?absolute maximu m ratings? may cause permanent damage to the device . these are stress ratings only, and functional operation of the device at these or any other condi tions beyond those indicated in the operational sec tions of the specifications is not implied. exposur e to absolute maximum rating conditions for extended periods may affect device reliability. dc electrical characteristics (v avdd = v dvdd = 3.0v to 3.6v, v iovdd = 1.7v to 3.6v, r l = 100 q 1% (differential), t a = -40 n c to +105 n c, unless otherwise noted. typical values are at v avdd = v dvdd = v iovdd = 3.3v, t a = +25 n c.) parameter symbol conditions min typ max units single-ended inputs (bws, int, cds, eqs, ms, pwdn , ssen, drs) high-level input voltage v ih1 0.65 x v iovdd v low-level input voltage v il1 0.35 x v iovdd v input current i in1 v in = 0v to v iovdd -10 +10 f a input clamp voltage v cl i cl = -18ma -1.5 v single-ended outputs (ws, sck, sd/cntl0, cntl1, cntl2/mclk) high-level output voltage v oh1 i out = -2ma dcs = 0 v iovdd - 0.3 v dcs = 1 v iovdd - 0.2 low-level output voltage v ol1 i out = 2ma dcs = 0 0.3 v dcs = 1 0.2 output short-circuit current i os v out = v gnd , dcs = 0 v iovdd = 3.0v to 3.6v 15 25 39 ma v iovdd = 1.7v to 1.9v 3 7 13 v out = v gnd , dcs = 1 v iovdd = 3.0v to 3.6v 20 35 63 v iovdd = 1.7v to 1.9v 5 10 21 downloaded from: http:///
gigabit multimedia serial link deserializer with lvds system interface max9268 _______________________________________________________________________________________ 3 dc electrical characteristics (continued) (v avdd = v dvdd = 3.0v to 3.6v, v iovdd = 1.7v to 3.6v, r l = 100 q 1% (differential), t a = -40 n c to +105 n c, unless otherwise noted. typical values are at v avdd = v dvdd = v iovdd = 3.3v, t a = +25 n c.) parameter symbol conditions min typ max units i 2 c and uart i/o, open-drain outputs (rx/sda, tx/scl, lock, err , gpio_) high-level input voltage v ih2 0.7 x v iovdd v low-level input voltage v il2 0.3 x v iovdd v input current i in2 v in = 0v to v iovdd (note 2) rx/sda, tx/scl -110 +1 f a lock, err , gpio_ -80 +1 low-level output voltage v ol2 i out = 3ma v iovdd = 1.7v to 1.9v 0.4 v v iovdd = 3.0v to 3.6v 0.3 differential output for reverse control channel (in+, in-) differential high output peak voltage, (v in+ ) - (v in- ) v roh no high-speed data transmission (figure 1) 30 60 mv differential low output peak voltage, (v in+ ) - (v in- ) v rol no high-speed data transmission (figure 1) -60 -30 mv differential inputs (in+, in-) differential high input threshold (peak) voltage, (v in+ ) - (v in- ) v idh(p) figure 2 40 90 mv differential low input threshold (peak) voltage, (v in+ ) - (v in- ) v idl(p) figure 2 -90 -40 mv input common-mode voltage ((v in+ ) + (v in- ))/2 v cmr 1 1.3 1.6 v differential input resistance (internal) r i 80 100 130 i three-level logic inputs (add0, add1) high-level input voltage v ih 0.7 x v iovdd v low-level input voltage v il 0.3 x v iovdd v mid-level input current i inm add0 and add1 open or connected to a driver with output in high impedance (note 3) -10 +10 f a input current i in add0 and add1 = high or low, pwdn = high or low -150 +150 f a input clamp voltage v cl i cl = -18ma -1.5 v lvds outputs (txout__, txclkout_) differential output voltage v od figure 3 250 450 mv change in v od between complementary output states d v od figure 3 25 mv output offset voltage v os figure 3 1.125 1.375 v change in v os between complementary output states d v os figure 3 25 mv downloaded from: http:///
gigabit multimedia serial link deserializer with lvds system interface max9268 4 ______________________________________________________________________________________ dc electrical characteristics (continued) (v avdd = v dvdd = 3.0v to 3.6v, v iovdd = 1.7v to 3.6v, r l = 100 q 1% (differential), t a = -40 n c to +105 n c, unless otherwise noted. typical values are at v avdd = v dvdd = v iovdd = 3.3v, t a = +25 n c.) ac electrical characteristics (v avdd = v dvdd = 3.0v to 3.6v, v iovdd = 1.7v to 3.6v, r l = 100 q 1% (differential), t a = -40 n c to +105 n c, unless otherwise noted. typical values are at v avdd = v dvdd = v iovdd = 3.3v, t a = +25 n c.) parameter symbol conditions min typ max units output short-circuit current i os v out = 0v or 3.6v 3.5ma lvds output -7.5 +7.5 ma 7ma lvds output -15 +15 magnitude of differential output short-circuit current i osd 3.5ma lvds output 7.5 ma 7ma lvds output 15 output high-impedance current i oz add0 and add1 = high or low, pwdn = high or low -0.5 +0.5 f a power supply worst-case supply current (figure 4) i wcs bws = low, f txclkout_ = 16.6mhz 142 180 ma bws = low, f txclkout_ = 33.3mhz 153 200 bws = low, f txclkout_ = 66.6mhz 179 240 bws = low, f txclkout_ = 104mhz 212 280 sleep-mode supply current i ccs 80 130 f a power-down current i ccz pwdn = gnd 19 70 f a parameter symbol conditions min typ max units lvds clock outputs (txclkout+, txclkout-) clock frequency f txclkout_ bws = gnd, v drs = v iovdd 8.33 16.66 mhz bws = gnd, drs = gnd 16.66 104 v bws = v iovdd , v drs = v iovdd 6.25 12.5 v bws = v iovdd , drs = gnd 12.5 78 i 2 c/uart port timing output rise time t r 30% to 70%, c l = 10pf to 100pf, 1k i pullup to iovdd (figure 5) 20 150 ns output fall time t f 70% to 30%, c l = 10pf to 100pf, 1k i pullup to iovdd (figure 5) 20 150 ns input setup time t set i 2 c only (figure 5) 100 ns input hold time t hold i 2 c only (figure 5) 0 ns switching characteristics cntl_ output rise-and-fall time t r , t f 20% to 80%, c l = 10pf, dcs = 1 (figure 6) v iovdd = 1.7v to 1.9v 0.5 3.1 ns v iovdd = 3.0v to 3.6v 0.3 2.2 20% to 80%, c l = 5pf, dcs = 0 (figure 6) v iovdd = 1.7v to 1.9v 0.6 3.8 v iovdd = 3.0v to 3.6v 0.4 2.4 lvds output rise time t r 20% to 80%, r l = 100 i (figure 3) 200 350 ps lvds output fall time t f 80% to 20%, r l = 100 i (figure 3) 200 350 ps downloaded from: http:///
gigabit multimedia serial link deserializer with lvds system interface max9268 _______________________________________________________________________________________ 5 ac electrical characteristics (continued) (v avdd = v dvdd = 3.0v to 3.6v, v iovdd = 1.7v to 3.6v, r l = 100 q 1% (differential), t a = -40 n c to +105 n c, unless otherwise noted. typical values are at v avdd = v dvdd = v iovdd = 3.3v, t a = +25 n c.) note 2: minimum i in due to voltage drop across the internal pullup resistor. note 3: measured in serial link bit times. bit time = 1/(30 x f txclkout_ ) for bws = gnd. bit time = 1/(40 x f txclkout_ ) for v bws = v iovdd . note 4: rising to rising-edge jitter can be twice as large. parameter symbol conditions min typ max units lvds output pulse position t pposn n = 0 to 6, t clk = 1/f txclkout_ , f txclkout_ = 104mhz (figure 7) f txclkout_ = 12.5mhz n/7 x t clk - 250 n/7 x t clk n/7 x t clk + 250 ps f txclkout_ = 33mhz n/7 x t clk - 200 n/7 x t clk n/7 x t clk + 200 f txclkout_ = 78mhz n/7 x t clk - 125 n/7 x t clk n/7 x t clk + 125 f txclkout_ = 104mhz n/7 x t clk - 100 n/7 x t clk n/7 x t clk + 100 lvds output enable time t lven from the last bit of the enable uart packet to v os = 1125mv 100 f s lvds output disable time t lvds from the last bit of the enable uart packet to v os = 0v 100 f s deserializer delay t sd figure 8 (note 4) 3540 bits reverse control-channel output rise time t r no forward-channel data transmission (figure 1) 180 400 ns reverse control-channel output fall time t f no forward-channel data transmission (figure 1) 180 400 ns lock time t lock figure 9 3.6 ms power-up time t pu figure 10 4.1 ms i 2 s output timing ws jitter t aj-ws t ws = 1/f ws , rising (falling) edge to falling (rising) edge (note 5) f ws = 48khz or 44.1khz 0.4e -3 x t ws 0.5e -3 x t ws ns f ws = 96khz 0.8e -3 x t ws 1e -3 x t ws f ws = 192khz 1.6e -3 x t ws 2e -3 x t ws sck jitter t aj-sck t sck = 1/f sck , rising edge to rising edge n ws = 16 bits, f ws = 48khz or 44.1khz 13e -3 x t sck 16e -3 x t sck ns n ws = 24 bits, f ws = 96khz 39e -3 x t sck 48e -3 x t sck n ws = 32 bits, f ws = 192khz 0.1 x t sck 0.13 x t sck audio skew relative to video t ask video and audio synchronized 3 x t ws 4 x t ws f s sck, sd, ws rise-and-fall time t r, t f 20% to 80% c l = 10pf, dcs = 1 0.3 3.1 ns c l = 5pf, dcs = 0 0.4 3.8 sd, ws valid time before sck t dvb t sck = 1/f sck (figure 11) 0.35 x t sck 0.5 x t sck ns sd, ws valid time after sck t dva t sck = 1/f sck (figure 11) 0.35 x t sck 0.5 x t sck ns downloaded from: http:///
gigabit multimedia serial link deserializer with lvds system interface max9268 6 ______________________________________________________________________________________ typical operating characteristics (v avdd = v dvdd = v iovdd = 3.3v, t a = +25 n c, unless otherwise noted.) txclkout_ frequency (mhz) total supply current (ma) 85 65 45 25 150 160 170 180 190 200 210140 5 105 total supply current vs. txclkout_ frequency (3-channel mode) max9268 toc01 prbs patternall equalizer modes all spread modes txclkout_ frequency (mhz) total supply current (ma) 65 50 35 20 150 160 170 180 190 200 210140 5 80 total supply current vs. txclkout_ frequency (4-channel mode) max9268 toc02 prbs patternall equalizer modes all spread modes output power spectrum vs. txclkout_ frequency (various max9268 spread) max9268 toc03 txclkout_ frequency (mhz) output power spectrum (dbm) 34.5 33.5 32.5 31.5 -90 -80 -70 -60 -50 -40 -30 -20 -10 -100 30.5 35.5 2% spread 0% spread 4% spread f txclkout_ = 33mhz output power spectrum vs. txclkout_ frequency (various max9268 spread) max9268 toc04 txclkout_ frequency (mhz) output power spectrum (dbm) 69 67 65 63 -90 -80 -70 -60 -50 -40 -30 -20 -10 -100 61 71 2% spread 0% spread f txclkout_ = 66mhz 4% spread maximum txclkout_ frequency vs. stp cable length (ber < 10 -9 ) max9268 toc05 stp cable length (m) maximum txclkout_ frequency (mhz) 15 10 5 20 40 60 80 100 120 0 0 20 optimumpe/eq settings no pe, 10.7dbequalization no pe, 5.2dbequalization ber can be as low as 10 -12 for cable lengths less than 10m maximum txclkout_ frequency vs. additional differential c l (ber < 10 -9 ) max9268 toc06 additional differential load capacitance (pf) 8 6 4 2 0 10 maximum txclkout_ frequency (mhz) 20 40 60 80 100 120 0 10m stp cable optimum pe/eq settings no pe, 10.7dbequalization no pe, 5.2db equalization ber can be as low as 10 -12 for c l < 4pf for optimum pe/eq settings downloaded from: http:///
gigabit multimedia serial link deserializer with lvds system interface max9268 _______________________________________________________________________________________ 7 pin description pin configuration gpio0 4 avdd 5 in+ 6 in- 7 agnd 8 eqs 9 gpio1 10 dvdd 11 gnd 12 bws 1 int 2 cds 3 33 32 31 30 29 28 27 26 25 ep 36 35 34 agndavdd gnd iovdd cntl2/mclk cntl1 sd/cntl0 sck ws pwdn tx/scl rx/sda agnd gnd iovdd add0add1 lock err ms ssen drs avdd agnd 3738 39 40 41 42 43 44 45 46 47 48 top view 2423 22 21 20 19 18 17 16 15 14 13 max9268 txout1+avdd agnd txout2- txout2+ txclkout- txclkout+ txout3- txout3+ txout0-txout0+ txout1- + tqfp pin name function 1 bws bus-width select. output width selection requires external pulldown or pullup resistor. set bws = low for 3-channel mode. set bws = high for 4-channel mode. 2 int interrupt input. requires external pulldown or pullup resistor. a transition on the max9268?s int input toggles the gmsl serializer?s int output. 3 cds control direction selection. control link direction selection input requires external pulldown or pullup resistor. set cds = low for f c on the gmsl serializer side of the serial link. set cds = high for f c on the max9268 side of the serial link. 4 gpio0 general-purpose i/o 0. open-drain, general-purpose input/output with internal 60k i (typ) pullup resistor to iovdd. gpio0 is high impedance during power-up and when pwdn = low. 5, 23, 32, 47 avdd 3.3v analog power supply. bypass avdd to agnd with 0.1 f f and 0.001 f f capacitors as close as possible to the device with the smaller capacitor closest to avdd. 6, 7 in+, in- differential cml input. differential input of the serial link. 8, 24, 31, 37, 48 agnd analog ground 9 eqs equalizer select input. eqs requires external pulldown or pullup resistor. the state of eqs latches upon power-up or when resuming from power-down mode ( pwdn = low). set eqs = low for 10.7db equalizer boost (eqtune = 1001). set eqs = high for 5.2db equalizer boost (eqtune = 0100). downloaded from: http:///
gigabit multimedia serial link deserializer with lvds system interface max9268 8 ______________________________________________________________________________________ pin description (continued) pin name function 10 gpio1 general-purpose i/o 1. open-drain general-purpose input/output with internal 60k i (typ) pullup resistor to iovdd. gpio1 is high impedance during power-up and when pwdn = low. 11 dvdd 3.3v digital power supply. bypass dvdd to gnd with 0.1 f f and 0.001 f f capacitors as close as possible to the device with the smaller capacitor closest to dvdd. 12, 22, 38 gnd digital and i/o ground 13 rx/sda receive/serial data. uart receive or i 2 c serial-data input/output with internal 30k i (typ) pullup to iovdd. in uart mode, rx/sda is the rx input of the max9268?s uart. in i 2 c mode, rx/sda is the sda input/output of the max9268?s i 2 c master. 14 tx/scl transmit/serial clock. uart transmit or i 2 c serial-clock output with internal 30k i (typ) pullup to iovdd. in uart mode, tx/scl is the tx output of the max9268?s uart. in i 2 c mode, tx/ scl is the scl output of the max9268?s i 2 c master. 15 pwdn power-down. active-low power-down input requires external pulldown or pullup resistor. 16 ws i 2 s word-select output 17 sck i 2 s serial-clock output 18 sd/cntl0 i 2 s serial-data/control output. disable i 2 s to use sd/cntl0 as an additional control output. 19 cntl1 control output 1. cntl1 is not active in 3-channel mode and remains low. to use cntl1, drive bws high (4-channel mode) and set discntl = 0. cntl1 is mapped from dout27. 20 cntl2/mclk control 2/mclk output. cntl2/mclk is not active in 3-channel mode and remains low. to use cntl2/mclk, drive bws high (4-channel mode). cntl2/mclk is mapped from dout28. cntl/mclk can also be used to output mclk (see the additional mclk output for audio applications section). 21, 39 iovdd i/o supply voltage. 1.8v to 3.3v logic i/o power supply. bypass iovdd to gnd with 0.1 f f and 0.001 f f capacitors as close as possible to the device with the smaller capacitor closest to iovdd. 25, 26, 29, 30, 33?36 txout_+, txout_- differential lvds data outputs. set bws = low (3-channel mode) to use txout0_ to txout2_. set bws = high (4-channel mode) to use txout0_ to txout3_. 27, 28 txclkout+, txclkout- differential lvds output for the lvds clock 40 add0 address selection input 0. three-level input to select the max9268?s device address (see table 2). the state of add0 latches upon power-up or when resuming from power-down mode ( pwdn = low). 41 add1 address selection input 1. three-level input to select the max9268?s device address (see table 2). the state of add1 latches upon power-up or when resuming from power-down mode ( pwdn = low). 42 lock open-drain lock output with internal 60k i (typ) pullup to iovdd. lock = high indicates plls are locked with correct serial-word-boundary alignment. lock = low indicates plls are not locked or incorrect serial-word-boundary alignment. lock remains low when the configuration link is active. lock is high impedance when pwdn = low. 43 err active-low, open-drain video data error output with internal 60k i (typ) pullup to iovdd. err goes low when the number of decoding errors during normal operation exceeds a pro- grammed error threshold, or when at least one prbs error is detected during prbs test. err is high impendence when pwdn = low. downloaded from: http:///
gigabit multimedia serial link deserializer with lvds system interface max9268 _______________________________________________________________________________________ 9 pin description (continued) functional diagram parallel to lvds video fifo audio rgb[17:0] rgb hs hs vs de cntl1/res 8b/10b decode/ unscramble serial to parallel reverse control channel uart/i 2 c cntl2 fcc acb vsde rgb[23:18] (4-ch) res/cntl1 (4-ch) txout0+/- txclkout+/- in+in- txout1+/- txout2+/- txout3+/- cntl1 (4-ch) cntl2/mclk (4-ch) sd/cntl0 tx/scl rx/sda sck ws max9268 tx rx/eq 7x pll sspll clk div cdr pll pin name function 44 ms mode select. control link mode-selection input requires an external pulldown or pullup resis- tor. set ms = low to select base mode. set ms = high to select bypass mode. 45 ssen spread-spectrum enable. serial link spread-spectrum enable input requires an external pull- down or pullup resistor. the state of ssen latches upon power-up or when resuming from power-down mode ( pwdn = low). set ssen = high for q 2% spread spectrum on the lvds and control outputs. set ssen = low to use the lvds and control outputs without spread spectrum. 46 drs data-rate select. data-rate range-selection input r equires an external pulldown or pullup resistor. the state of drs latches upon power-up or when resu ming from power-down mode ( pwdn = low). set drs = high for txclkout_ frequencies of 8 .33mhz to 16.66mhz (3-channel mode), or 6.25mhz to 12.5mhz (4-channel mode). set drs = low for txclkout_ frequencies of 16.66mhz to 104mhz (3-channel mode), or 12.5mhz to 78mhz (4- channel mode). ? ep exposed pad. ep internally connected to agnd. must externally connect ep to the plane supplying agnd for proper thermal and electrical performance. downloaded from: http:///
gigabit multimedia serial link deserializer with lvds system interface max9268 10 _____________________________________________________________________________________ figure 1. reverse control-channel output parameters figure 2. test circuit for differential input measurement max9268 reverse control-channel transmitter in+ in- in- in+ in+ in- v od r l /2 r l /2 v cmr v cmr v roh (in+) - (in-) t r 0.1 x v rol 0.9 x v rol t f v rol 0.9 x v roh 0.1 x v roh v in+ r l /2 r l /2 c in c in v id(p) in+ in- v id(p) = | v in+ - v in- | v cmr = (v in+ + v in- )/2 v in- _ + _ _ + downloaded from: http:///
gigabit multimedia serial link deserializer with lvds system interface max9268 ______________________________________________________________________________________ 11 figure 3. lvds output parameters figure 4. worst-case pattern output figure 5. i 2 c timing parameters txout_-, txclkout- v od v os gnd r l /2 r l /2 txout_+ txclkout+ txout_+ txclkout+ (txout_+) - (txout_-) (txclkout+) - (txclkout-) v os(-) v os(+) ((txclkout+) + (txclkout-))/2 ((txout_+) + (txout_-))/2 v os(-) v od(-) v od(-) t r v od = 0v d v os = |v os(+) - v os(-) | d v od = |v od(+) - v od(-) | v od (+) txout_- txclkout- t f txclkout+ txclkout- txout0+ to txout3+ txout0- to txout3- cntl_ p t r p s s t hold t f t set tx/ scl rx/ sda downloaded from: http:///
gigabit multimedia serial link deserializer with lvds system interface max9268 12 _____________________________________________________________________________________ figure 6. single-ended output rise-and-fall times figure 7. lvds output pulse position measurement figure 8. deserializer delay figure 10. power-up delay figure 9. lock time figure 11. output i 2 s timing parameters 0.8 x v i0vdd 0.2 x v i0vdd t f t r c l single-ended output load max9268 expanded time scale n first bit in+/in- txout_+/ txout_- txclkout+/- n+1 n-1 n first bit t sd n+2... in+ - in-lock t lock pwdn must be high v oh (txclkout+) - (txclkout-) (txout_+) - (txout_-) t ppos0 t ppos1 t ppos2 t ppos3 t ppos4 t ppos5 t ppos6 in+/- lock t pu pwdn v oh v ih1 ws t dva t dvb t dva t f t dvb t r sck sd downloaded from: http:///
gigabit multimedia serial link deserializer with lvds system interface max9268 ______________________________________________________________________________________ 13 detailed description the max9268 deserializer with lvds system inter- face utilizes maxim?s gmsl technology. the max9268 deserializer pairs with any gmsl serializer to form a complete digital serial link for joint transmission of high- speed video, audio, and bidirectional control data. the max9268 allows a maximum serial payload data rate of 2.5gbps for greater than 15m of stp cable. the deserializer operates up to 104mhz for 3-channel lvds or 78mhz for 4-channel lvds. the operating frequency range supports display panels from qvga (320 x 240) up to wxga (1280 x 800) and higher with 24-bit color. the 3-channel mode outputs an lvds clock, three lanes of lvds data (21 bits), uart control signals, and one i 2 s audio channel (consisting of three sig- nals). the 4-channel mode outputs an lvds clock, four lanes of lvds data (28 bits), uart control signals, one i 2 s audio channel, and control signals. the i 2 s interface supports sample rates from 8khz to 192khz and audio word lengths of 4 to 32 bits. the embed- ded control channel forms a full-duplex, differential, 100kbps to 1mbps uart link between the serializer and deserializer. an ecu or f c can be located on the serializer side of the link (typical for video display), on the max9268 side of the link (typical for image sensing), or on both sides. in addition, the control channel enables ecu/ f c control of peripherals in the remote side, such as backlight control, grayscale gamma correction, camera module, and touch screen. base-mode com- munication with peripherals uses either i 2 c or the gmsl uart format. a bypass mode enables full-duplex com- munication using custom uart formats. the max9268 channel equalizer, along with the serializer preemphasis, extends the link length and enhances the link reliability. spread spectrum is avail- able to reduce emi on the lvds and control outputs of the max9268. the serial input complies with iso 10605 and iec 61000-4-2 esd protection standards. register mapping the f c configures various operating conditions of the gmsl serializer and the max9268 through internal registers. the default device addresses are stored in reg- isters 0x00 and 0x01 of both the gmsl serializer and the max9268 (table 1). write to the 0x00 and 0x01 registers in both devices to change the device address of the gmsl serializer or the max9268. table 1. power-up default register map (see table 12) register address (hex) power-up default (hex) power-up default settings (msb first) 0x00 0x40, 0x44, 0x48 0x80, 0x84, 0x88, 0xc0, 0xc4, 0xc8 serid = xx00xx0, serializer device address is determined by add1 and add0 (table 2) reserved = 0 0x01 0x50, 0x54, 0x58, 0x90, 0x94, 0x98, 0xd0, 0xd4, 0xd8 desid =xx01xx0, deserializer device address is determined by add1 and add0 (table 2) reserved = 0 0x02 0x1f or 0x5f ss = 00 (ssen = low), ss = 01 (ssen = high), spread-spectrum settings depend on ssen pin state at power-up reserved = 0 audioen = 1, i 2 s channel enabled prng = 11, automatically detect the pixel clock range srng = 11, automatically detect serial-data rate 0x03 0x00 autofm = 00, calibrate spread-modulation rate only once after locking reserved = 0 sdiv = 00000, autocalibrate sawtooth divider downloaded from: http:///
gigabit multimedia serial link deserializer with lvds system interface max9268 14 _____________________________________________________________________________________ table 1. power-up default register map (see table 12) (continued) register address (hex) power-up default (hex) power-up default settings (msb first) 0x04 0x03 or 0x13 locked = 0, lock output is low (read only) outenb = 0, outputs enabled prbsen = 0, prbs test disabled sleep = 0 or 1, sleep setting default depends on cds and ms pin state at power-up (see the link startup procedure section) inttype = 00, base mode uses i 2 c revccen = 1, reverse control channel active (sending) fwdccen = 1, forward control channel active (receiving) 0x05 0x24 or 0x29 i2cmethod = 0, i 2 c master sends the register address hpftune = 01, 3.75mhz equalizer highpass cutoff frequency pdhf = 0, high-frequency boosting disabled eqtune = 0100 (eqs = high, 5.2db), eqtune = 1001 (eqs = low, 10.7db), eqtune default setting depends on eqs pin state at power-up 0x06 0x0f reserved = 0 autorst = 0, error registers/output autoreset disabled disint = 0, int transmission enabled int = 0, int output is low (read only) gpio1out = 1, gpio1 output set to high gpio1 = 1, gpio1 input = high (read only) gpio0out = 1, gpio0 output set to high gpio0 = 1, gpio0 input = high (read only) 0x07 0x54 reserved = 01010100 0x08 0x30 reserved = 00110000 0x09 0xc8 reserved = 11001000 0x0a 0x12 reserved = 00010010 0x0b 0x20 reserved = 00100000 0x0c 0x00 errthr = 00000000, error threshold set to zero for decoding errors 0x0d 0x00 (read only) decerr = 00000000, zero decoding errors detected 0x0e 0x00 (read only) prbserr = 00000000, zero prbs errors detected 0x12 0x00 mclksrc = 0, mclk is derived from pclk (see table 5) mclkdiv = 0000000, mclk output is disabled 0x13 0xx0 reserved = xxx reserved = 10000 0x14 0x01 reserved = 00 forcelvds = 0, normal lvds operation dcs = 0, normal cmos driver current strength discntl1 = 0, serial-data bit 27 is mapped to cntl1 disres = 0, serial-data bit 27 is mapped to res ilvds = 01, 3.5ma lvds output current downloaded from: http:///
gigabit multimedia serial link deserializer with lvds system interface max9268 ______________________________________________________________________________________ 15 x = don?t care. * add0 and add1 affect the default device address values stored in the max9268 only. the default device address values stored in the gmsl serializer may differ (see the 3-level inputs for default device address section). ** x = 0 for the serializer address, x = 1 for the deserializer address. table 1. power-up default register map (see table 12) (continued) table 2. deserializer device address defaults (register 0x01) register address (hex) power-up default (hex) power-up default settings (msb first) 0x1e 0x04 (read only) id = 00000100, device id is 0x04 0x1f 0x0x (read only) reserved = 000 caps = 0, not hdcp capable revision = xxxx pin device address* (bin) serializer device address* (hex) deserializer device address* (hex) add1 add0 d7 d6 d5 d4 d3 d2 d1 d0 low low 1 0 0 x** 0 0 0 r /w 80 90 low high 1 0 0 x** 0 1 0 r /w 84 94 low open 1 0 0 x** 1 0 0 r /w 88 98 high low 1 1 0 x** 0 0 0 r /w c0 d0 high high 1 1 0 x** 0 1 0 r /w c4 d4 high open 1 1 0 x** 1 0 0 r /w c8 d8 open low 0 1 0 x** 0 0 0 r /w 40 50 open high 0 1 0 x** 0 1 0 r /w 44 54 open open 0 1 0 x** 1 0 0 r /w 48 58 downloaded from: http:///
gigabit multimedia serial link deserializer with lvds system interface max9268 16 _____________________________________________________________________________________ typical bitmapping and bus-width selection the lvds output has two selectable widths: 3-channel and 4-channel. the max9268 outputs 3- or 4-channel lvds (table 3). serial data is mapped to outputs on the max9268 according to figures 12 and 13. in 3-chan- nel mode, txout3_ and cntl1, cntl2/mclk are not available. for both modes, the sd/cntl0, sck, and ws pins are for i 2 s audio when audio is enabled. with audio disabled, sd/cntl0 becomes control signal cntl0. the max9268 outputs clock rates from 8.33mhz to 104mhz for 3-channel mode and 6.25mhz to 78mhz for 4-channel mode. serial link signaling and data format the gmsl high-speed serial link uses cml signaling with programmable preemphasis and ac-coupling. the gmsl deserializer uses ac-coupling and programmable channel equalization. when using both the preemphasis and equalization, including internally generated over- head bits, the gmsl link operates up to 3.125gbps over stp cable lengths of 15m or greater. the payload data rate, which is the data rate available to the user or the data rate after subtracting overhead, is 2.5gbps. the gmsl serializer scrambles and encodes the input data and sends the 8b/10b coded signal through the serial link. the max9268 deserializer recovers the embedded serial clock and then samples, decodes, and descrambles before outputting the data. figures 14 and 15 show the serial-data packet format after unscrambling and 8b/10b decoding. in 3-channel or 4-channel mode, 21 or 28 bits map to the txout_ _ lvds outputs. serial- data bits 27 and 28 map to control outputs in 4-channel mode. the audio channel bit (acb) contains an encoded audio signal derived from the three i 2 s signals (sd/ cntl0, sck, and ws). the forward control-channel (fcc) bit carries the forward control data. the last bit (pcb) is the parity bit of the previous 23 or 31 bits. * see the reserved bit (res)/cntl1 section for details. table 3. bus-width selection using bws output bits 3-channel mode (bws = low) 4-channel mode (bws = high) typical bitmapping auxiliary signals mapping typical bitmapping auxiliary signals mapping dout[0:5] r[0:5] ? r[0:5] ? dout[6:11] g[0:5] ? g[0:5] ? dout[12:17] b[0:5] ? b[0:5] ? dout[18:20] hs, vs, de ? hs, vs, de ? dout[21:22] not used not used r6, r7 ? dout[23:24] not used not used g6, g7 ? dout[25:26] not used not used b6, b7 ? dout27 not used not used res* cntl1* dout28 not used not used ? cntl2/mclk sd ? sd/cntl0 ? sd/cntl0 downloaded from: http:///
gigabit multimedia serial link deserializer with lvds system interface max9268 ______________________________________________________________________________________ 17 figure 12. lvds output timing figure 13. typical panel clock and bit assignment dout1 cycle n txout0+ /txout0- txclkout+ txclkout- txout1+/txout1-txout2+/txout2- dout0 dout6 dout5 dout4 dout3 dout2 dout1 dout0 dout8 dout7 dout13 dout12 dout11 dout10 dout9 dout8 dout7 dout15 dout14 dout20 dout19 dout18 dout17 dout16 dout15 dout14 txout3+/txout3- cntl1 dout22 dout21 dout27 cntl2/mclk dout28 sd/cntl0 *only when i 2 s is disabled. sd* dout27 dout26 dout25 dout24 dout23 dout22 dout21 cycle n-1 r1 cycle n-1 cycle n txout0+/txout0- txclkout+ txclkout- txout1+/txout1-txout2+/txout2- r0 g0 r5 r4 r3 r2 r1 r0 g2 g1 b1 b0 g5 g4 g3 g2 g1 b3 b2 de vs hs b5 b4 b3 b2 txout3+/txout3- r7 r6 res b7 b6 g7 g6 r7 r6 downloaded from: http:///
gigabit multimedia serial link deserializer with lvds system interface max9268 18 _____________________________________________________________________________________ reserved bit (res)/cntl1 in 4-channel mode, the max9268 deserializes serial- data bit 27 to both res and cntl1 by default (both discntl and disres = 0). setting disres (d2 of register 0x14) = 1 forces res low. setting discntl1 (d3 of register 0x14) = 1 forces cntl1 low. reverse control channel the gmsl serializer uses the reverse control channel to receive i 2 c/uart and interrupt signals from the max9268 in the opposite direction of the video stream. the reverse control channel and forward video data coexist on the same twisted pair forming a bidirec- tional link. the reverse control channel operates inde- pendently from the forward control channel. the reverse control channel is available 500 f s after power-up. the gmsl serializer temporarily disables the reverse control channel for 350 f s after starting/stopping the forward serial link. data-rate selection the max9268 uses the drs input to set the txclkout_ frequency. set drs high for a txclkout_ frequency of 6.25mhz to 12.5mhz (4-channel mode), or 8.33mhz to 16.66mhz (3-channel mode). set drs low for normal operation with a txclkout_ frequency of 12.5mhz to 78mhz (4-channel mode), or 16.66mhz to 104mhz (3-channel mode). audio channel the i 2 s audio channel supports audio sampling rates from 8khz to 192khz and audio word lengths from 4 bits to 32 bits. the audio bit clock (sck) does not have to be synchronized with txclkout_. the gmsl serializer automatically encodes audio data into a single bit stream figure 14. 3-channel mode serial link data format figure 15. 4-channel mode serial link data format note: typical locations of the rgb data and control signals. dout0 lvdsdata (3 channels) dout1 dout17 dout18 dout19 dout20 acb fcc pcb 24 bits audio channel bit forward control- channel bit packet parity check bit r0 r1 b5 hs vs de dout21 lvdsdata (txout3_) dout22 dout25 dout26 dout27 dout28 acb fcc pcb 32 bits audio channel/cntl0 bit forward control- channel bit packet parity check bit r6 r7 b6 dout24 g7 dout23 g6 b7 cntl2 res/cntl1* dout1 lvdsdata (txout[2:0]_) dout18 dout19 dout20 r1 dout0 r0 hs dout17 b5 vs de *dout27 outputs to lvds data (txout3_) and/or external pin (cntl1). note: typical locations of the lvds rgb data and control signals. downloaded from: http:///
gigabit multimedia serial link deserializer with lvds system interface max9268 ______________________________________________________________________________________ 19 synchronous with txclkout_. the max9268 deserial- izer decodes the audio stream and stores audio words in a fifo. audio rate detection uses an internal oscillator to continuously determine the audio data rate and output the audio in i 2 s format. the audio channel is enabled by default. when the audio channel is disabled, the audio data input (sd) on the serializer becomes a control input (cntl0) and sd/cntl0 becomes a control output on the deserializer. low txclkout_ frequencies limit the maximum audio sampling rate. table 4 lists the maximum audio sampling rate for various txclkout_ frequencies. spread-spectrum settings do not affect the i 2 s data rate or ws clock frequency. additional mclk output for audio applications some audio dacs such as the max9850 do not require a synchronous main clock (mclk), while other dacs require mclk to be a specific multiple of ws. if the audio dac chip needs the mclk to be a multiple of ws, use an external pll to regenerate the required mclk from ws or sck. for audio applications that have ws synchronous to txclkout_, the max9268 provides a divided clock output on cntl2/mclk at the expense of one less control line in 4-channel mode (3-channel mode is not affected). by default, cntl2/mclk operates as a con- trol data output, and mclk is turned off. set mclkdiv (max9268 register 0x12, d[6:0]) to a nonzero value to enable the mclk output. set mclkdiv to 0x00 to disable mclk and set cntl2/mclk as a control data output. the output mclk frequency is: src mclk f f mclkdiv = where: f src = the mclk source frequency (table 5) mclkdiv = the divider ratio from 1 to 127 choose mclkdiv values such that f mclk is not greater than 60mhz. mclk frequencies derived from txclkout_ (msclksrc = 0) are not affected by spread-spectrum settings in the max9268. however, enabling spread spectrum in the gmsl serializer intro- duces spread spectrum into mclk. spread-spectrum settings of either device do not affect mclk frequencies derived from the internal oscillator. the internal oscilla- tor frequency ranges from 100mhz to 150mhz over all process corners and operating conditions. table 4. maximum audio ws frequency (khz) for various txclkout_ frequencies table 5. f src settings word length (bits) txclkout_ frequency (drs = low) (mhz) txclkout_ frequency (drs = high) (mhz) 12.5 15 16.6 > 20 6.25 7.5 8.33 > 10 8 > 192 > 192 > 192 > 192 > 192 > 192 > 192 > 192 16 > 192 > 192 > 192 > 192 > 192 > 192 > 192 > 192 18 185.5 > 192 > 192 > 192 185.5 > 192 > 192 > 192 20 174.6 > 192 > 192 > 192 174.6 > 192 > 192 > 192 24 152.2 182.7 > 192 > 192 152.2 182.7 > 192 > 192 32 123.7 148.4 164.3 > 192 123.7 148.4 164.3 > 192 mclksrc setting (register 0x12, d7) data-rate setting bus-width setting mclk source frequency (f src ) 0 high speed 3-channel mode 3 x f txclkout_ 4-channel mode 4 x f txclkout_ low speed 3-channel mode 6 x f txclkout_ 4-channel mode 8 x f txclkout_ 1 ? ? internal oscillator (120mhz, typ) downloaded from: http:///
gigabit multimedia serial link deserializer with lvds system interface max9268 20 _____________________________________________________________________________________ control channel and register programming the control channel is available for the f c to send and receive control data over the serial link simultane ously with the high-speed data, to program registers on the li nk serial- izer/deserializer or to program peripherals. config uring the cds pin allows a f c to control the link from the side of the serializer or deserializer, or with dual f cs from both sides, to support a wide variety of applications. the control channel runs in base mode or bypass mod e according to the mode-selection (ms) input of the d evice connected to the f c. in base mode, the control-channel transactions are half-duplex and in bypass mode the y are full-duplex. base mode in base mode the f c is the host, and in order to access the registers of the serializer or deserializer it must use the gmsl uart format and protocol. the f c accesses peripherals with an i 2 c interface by sending gmsl uart packets, which are converted to i 2 c by the serializer or deserializer on the remote side of the link. the f c communicates with a uart peripheral in base mode (through inttype register settings) using the gmsl uart protocol. the device addresses of the gmsl serializ er and max9268 in base mode are programmable. the default max9268 device address is determined by add0 and add1 upon power-up, or after returning from a power - down state (table 2). when the peripheral interface uses i 2 c (default), the gmsl serializer/max9268 convert packets to i 2 c that have device addresses different from those of the gmsl serializ er or max9268. the converted i 2 c bit rate is the same as the original uart bit rate. the gmsl serializer embeds control signals going to the max9268 in the high-speed forward link. the max9268 uses a proprietary differential line coding to send signals back towards the serializer. the speed of the contr ol chan- nel ranges from 100kbps to 1mbps in both directions . the gmsl serializer and max9268 deserializer automatica lly detect the control-channel bit rate in base mode. p acket bit rates can vary up to 3.5x from the previous bit rat e (see the changing the clock frequency section ). figure 16 shows the uart protocol for writing and reading in base m ode between the f c and the gmsl serializer/max9268. figure 17 shows the uart data format. figures 18 an d 19 detail the formats of the sync byte (0x79) and the ack byte (0xc3). the f c and the connected slave chip gen- erate the sync byte and ack byte, respectively. eve nts such as device wake-up and interrupt generate trans itions on the control channel that should be ignored by th e f c. data written to the gmsl serializer/max9268 registe rs do not take effect until after the acknowledge byte is sent. this allows the f c to verify write commands received with- out error, even if the result of the write command directly affects the serial link. the slave uses the sync by te to synchronize with the host uart data rate automatica lly. if the int or ms inputs of the max9268 toggle while th ere is control-channel communication, the control-channel com- munication can be corrupted since int has priority on the control channel. in the event of a missed acknowled ge, the f c should assume there was an error in the packet wh en the slave device receives it, or that an error occu rred during the response from the slave device. in base mode, t he f c must keep the uart tx/rx lines high for 16 bit time s before sending a new packet. as shown in figure 20, the remote-side device conve rts the packets going to or coming from the peripherals from the uart format to the i 2 c format and vice versa. the remote device removes the byte number count and add s or receives the ack between the data bytes of i 2 c. the i 2 c?s data rate is the same as the uart data rate. figure 16. gmsl uart protocol for base mode write data format sync dev addr + r/w reg addr number of bytes sync dev addr + r/w reg addr number of bytes byte 1 byte n ack byte n byte 1 ack master reads from slave read data frmat master writes to slave master writes to slave master reads from slave downloaded from: http:///
gigabit multimedia serial link deserializer with lvds system interface max9268 ______________________________________________________________________________________ 21 figure 17. gmsl uart data format for base mode figure 18. sync byte (0x79) figure 19. ack byte (0xc3) figure 20. format conversion between gmsl uart and i 2 c with register address (i2cmethod = 0) start d0 d1 d2 d3 d4 d5 d6 d7 parity stop 1 uart frame frame 1 frame 2 frame 3 stop start stop start 11 sync frame register address number of bytes device id + wr data 0 dev id a 11 11 11 11 data n 11 11 s 1 1 1 ack frame 7 : master to slave 8 gmsl serializer/max9268 peripheral w 1 reg addr 8 a 1 1 8 1 11 sync frame register address number of bytes device id + rd 11 11 11 11 ack frame data 0 11 data n 11 uart-to-i 2 c conversion of write packet (i2cmethod = 0) uart-to-i 2 c conversion of read packet (i2cmethod = 0) s: start p: stop a: acknowledge : slave to master data 0 a data n a p dev id a s 1 1 7 w 1 dev id a s 1 1 7 r 1 data n p 1 8 a 1 data 0 8 a 1 reg addr 8 a 1 f c gmsl serializer/max9268 f c gmsl serializer/max9268 gmsl serializer/max9268 peripheral start d0 1 0 0 1 1 1 1 0 d1 d2 d3 d4 d5 d6 d7 parity stop start d0 1 1 0 0 0 0 1 1 d1 d2 d3 d4 d5 d6 d7 parity stop downloaded from: http:///
gigabit multimedia serial link deserializer with lvds system interface max9268 22 _____________________________________________________________________________________ interfacing command-byte-only i 2 c devices the gmsl serializer and max9268 uart-to-i 2 c conversion interfaces with devices that do not require register addresses, such as the max7324 gpio expand- er. in this mode, the i 2 c master ignores the register address byte and directly reads/writes the subsequent data bytes (figure 21). change the communication method of the i 2 c master using the i2cmethod bit. i2cmethod = 1 sets command-byte-only mode, while i2cmethod = 0 sets normal mode where the first byte in the data stream is the register address. bypass mode in bypass mode, the gmsl serializer/max9268 ignore uart communications. the f c is thereby free to communicate with the peripherals using its own uart protocol without concern that communication traffic inadvertently misprograms the gmsl serializer or max9268. the f c cannot access the gmsl serializer/ max9268 registers in this mode. peripherals accessed through the forward control channel using the uart interface need to handle at least one txclkout_ period of jitter due to the asynchronous sampling of the uart signal by txclkout_. set ms = high to put the control channel into bypass mode. for applications with the f c connected to the deserializer (cds is high), there is a 1ms wait time between setting ms high and the bypass control channel being active. there is no delay time when switching to bypass mode when the f c is connected to the serializer (cds = low). bypass mode accepts bit rates down to 28kbps in the forward direction (serializer to deserial- izer), and 7.7kbps in the reverse direction (deserializer to serializer). see the interrupt control section for interrupt functionality limitations. the control-channel data pattern should not be held low longer than 100s if interrupt control is used. interrupt control the int pin of the gmsl serializer is the interrupt output and the int pin of the max9268 is the interrupt input. the interrupt output on the gmsl serializer follows the transitions at the interrupt input, even during reverse- channel communication or loss of lock. this interrupt function supports remote-side functions such as touch- screen peripherals, remote power-up, or remote moni- toring. interrupts that occur during periods where the reverse control channel is disabled, such as link startup/ shutdown, are automatically resent once the reverse control channel becomes available again. bit d4 of register 0x06 in the max9268 also stores the interrupt input state. the int output of the gmsl serializer is low after power-up. in addition, the f c can set the int output of the serializer by writing to the setint register bit. in normal operation, the state of the interrupt output changes when the interrupt input on the max9268 toggles. do not send a logic-low value longer than 100 f s in either base or bypass mode to ensure proper interrupt functionality. figure 21. format conversion between gmsl uart and i 2 c with register address (i2cmethod = 1) : master to slave gmsl serializer/max9268 gmsl serializer/max9268 gmsl serializer/max9268 uart-to-i 2 c conversion of read packet (i2cmethod = 1) uart-to-i 2 c conversion of write packet (i2cmethod = 1) f c gmsl serializer/max9268 f c sync frame 11 11 11 11 11 11 11 11 11 11 11 11 11 11 device id + rd register address number of bytes sync frame device id + wr register address number of bytes data 0 data n ack frame ack frame data 0 data n data n a data 0 w a dev id s a p peripheralperipheral s 1 1 1 8 8 8 1 11 1 7 1 1 8 1 1 1 7 dev id r a a a p data 0 data n : slave to master s: start p: stop a: acknowledge downloaded from: http:///
gigabit multimedia serial link deserializer with lvds system interface max9268 ______________________________________________________________________________________ 23 line equalizer the max9268 includes an adjustable line equalizer t o further compensate cable attenuation at high freque ncies. the cable equalizer has 12 selectable levels of com pensa- tion, from 2.1db to 13db (table 6). the eqs input s elects the default equalization level at power-up. the sta te of eqs is latched upon power-up or when resuming from powe r- down mode. to select other equalization levels, set the corresponding register bits in the max9268 (0x05 d[ 3:0]). use equalization in the max9268, together with pree mpha- sis in the gmsl serializer, to create the most reli able link for a given cable. spread spectrum to reduce the emi generated by the transitions on t he serial link and outputs of the max9268, both the gmsl seri al- izer and max9268 support spread spectrum. turning o n spread spectrum on the gmsl serializer spreads the serial data and the max9268 outputs. do not enable spread for both the gmsl serializer and the max9268. the two s elect- able spread-spectrum rates at the max9268 outputs a re q 2% and q 4% (table 7). set the max9268 ssen input high to select 2% spread at power-up, and ssen input low to select no spread at power-up. the state of ssen is latched upon power-u p or when resuming from power-down mode. turning on spread spectrum on the gmsl serializer o r the max9268 does not affect the audio data stream. chan ges in the gmsl serializer spread settings only affect the max9268 mclk output if it is derived from txclkout_ (mclksrc = 0). the max9268 includes a sawtooth divider to control the spread-modulation rate. autodetection or manual pro gram- ming of the txclkout_ operation range guarantees a spread-spectrum modulation frequency within 20khz t o 40khz. additionally, manual configuration of the sa wtooth divider (sdiv, 0x03 d[4:0]) allows the user to set a modula- tion frequency according to the txclkout_ frequency . always keep the modulation frequency between 20khz to 40khz to ensure proper operation. manual programming of the spread-spectrum divider the modulation rate for the max9268 relates to the txclkout_ frequency as follows: ( ) txclkout_ m f f 1 drs mod sdiv = + where: f m = modulation frequency drs = drs input value (0 or 1) f txclkout_ = lvds clock frequency mod = modulation coefficient given in table 8 sdiv = 5-bit sdiv setting, manually programmed by the f c to program the sdiv setting, first look up the modu lation coefficient according to the spread-spectrum settin gs. table 6. cable equalizer boost levels table 7. lvds and control output spread rates table 8. modulation coefficients and maximum sdiv settings boost setting (0x05 d[3:0]) typical boost gain (db) 0000 2.1 0001 2.8 0010 3.4 0011 4.2 0100 5.2 power-up default (eqs = high) 0101 6.2 0110 7 0111 8.2 1000 9.4 1001 10.7 power-up default (eqs = low) 1010 11.7 1011 13 ss spread (%) 00 no spread spectrum. power-up default when ssen = low. 01 q 2% spread spectrum. power-up default when ssen = high. 10 no spread spectrum 11 q 4% spread spectrum spread- spectrum setting (%) modulation coefficient (dec) sdiv upper limit (dec) 4 208 15 2 208 30 downloaded from: http:///
gigabit multimedia serial link deserializer with lvds system interface max9268 24 _____________________________________________________________________________________ solve the above equation for sdiv using the desired pixel clock and modulation frequencies. if the calculated sdiv value is larger than the maximum allowed sdiv value in table 8, set sdiv to the maximum value. sleep mode the gmsl serializer/max9268 include low-power sleep mode to reduce power consumption on the device not attached to the f c (the max9268 in lcd applications and the gmsl serializer in camera applications). set th e corre- sponding remote ic?s sleep bit to 1 to initiate sle ep mode. the gmsl serializer sleeps immediately after settin g its sleep = 1. the max9268 sleeps after serial link ina ctivity or 8ms (whichever arrives first) after setting its sleep = 1. see the link startup procedure section for details on wak- ing up the device for different f c and starting conditions. the f c side device cannot enter into sleep mode. if an attempt is made to program the f c side device for sleep, the sleep bit remains 0. use the power-down mode to bring the f c side device into a low-power state. power-down mode the max9268 includes a power-down mode to further reduce power consumption. set pwdn low to enter power- down mode. while in power-down mode, the outputs of the device remain high impedance. entering power-do wn mode resets the internal registers of the device. i n addition, upon exiting power-down mode, the max9268 relatches the state of ssen, eqs, drs, and add_. configuration link mode the gmsl includes a low-speed configuration link to allow control-data connection between the two devices in the absence of a valid clock input. in either display o r camera applications, the configuration link can be used to program equalizer/preemphasis or other registers before est ablish- ing the video link. an internal oscillator provides a clock for establishing the serial configuration link betw een the gmsl serializer and the max9268. set clinken = 1 on the gmsl serializer to turn on the configuration li nk. the configuration link remains active as long as the vi deo link has not been enabled. the video link overrides the configu- ration link and attempts to lock when seren = 1. link startup procedure table 9 lists four startup cases for video-display applica- tions. table 10 lists two startup cases for image-s ensing applications. in either video-display or image-sens ing applications, the control link is always available after the high-speed data link or the configuration link is e stablished and the gmsl serializer/max9268 registers or periph erals are ready for programming. video-display applications for a video-display application with a remote displ ay unit, connect the f c to the gmsl serializer and set cds = low for both the gmsl serializer and the max9268. table 9 summarizes the four startup cases based on the sett ings of autos and ms. case 1: autostart mode after power-up or when pwdn transitions from low to high for both the serializer and deserializer, the serial link establishes whether a stable clock is present. the gmsl serializer locks to the clock and sends the serial data to the max9268. the max9268 then detects activity on the s erial link and locks to the input serial data. case 2: standby start mode after power-up or when pwdn transitions from low to high for both the serializer and deserializer, the max92 68 starts up in sleep mode, and the gmsl serializer stays in standby mode (does not send serial data). use the f c and program the serializer to set seren = 1 to establish a vide o link or clinken = 1 to establish the configuration link. after locking to a stable clock (for seren = 1) or the in ternal oscillator (for clinken = 1), the serializer sends a wake- up signal to the max9268. the max9268 exits sleep m ode after locking to the serial data and sets sleep = 0 . if after 8ms the max9268 does not lock to the input serial d ata, the deserializer goes back to sleep and the internal sl eep bit remains set (sleep = 1). case 3: remote side autostart mode after power-up or when pwdn transitions from low to high, the remote device (max9268) starts up and tries to lock to an incoming serial signal with sufficient power. the host side (gmsl serializer) is in standby mode and does not try to establish a link. use the f c and program the serializer to set seren = 1 (and apply a stable clock signal) to establish a video link, or clinken = 1 to establ ish the configuration link. in this case, the max9268 ignor es the short wake-up signal sent from the gmsl serializer. case 4: remote side in sleep mode after power-up or when pwdn transitions from low to high, the remote device (max9268) starts up in sleep mode . the high-speed link establishes automatically after the gmsl serializer powers up with a stable clock signa l and sends a wake-up signal to the max9268. use this mod e in applications where the max9268 powers up before the gmsl serializer. downloaded from: http:///
gigabit multimedia serial link deserializer with lvds system interface max9268 ______________________________________________________________________________________ 25 table 9. startup selection for display applications (cds = low) figure 22. state diagram, cds = low (lcd application) case autos (gmsl serializer) gmsl serializer power-up state ms (max9268) max9268 power-up state link startup mode 1 low serialization enabled low normal (sleep = 0) both devices power up with serial link active (autostart). 2 high serialization disabled high sleep mode (sleep = 1) serial link is disabled and the max9268 powers up in sleep mode. set seren = 1 or clinken = 1 in the gmsl serializer to start the serial link and wake up the max9268. 3 high serialization disabled low normal (sleep = 0) both devices power up in normal mode with the serial link disabled. set seren = 1 or clinken = 1 in the gmsl serializer to start the serial link. 4 low serialization enabled high in sleep mode (sleep = 1) max9268 starts in sleep mode. link autostarts upon gmsl serializer power-up. use this case when the max9268 powers up before the serializer. sleep ms pin setting low high 01 sleep bit power-up value config link operating program registers power-off high to low sleep = 1, video link or config link not locked after 8ms power-on idle wake-up signal serial port locking signal detected config link unlocked config link locked video link locked video link unlocked 0 sleep 0 sleep all states int changes from low to high or send int to pwdn = low or pwdn = high,power-on power-down or power-off serial link activity stops or 8ms elapses after f c sets sleep = 1 video link operating prbsen = 0prbsen = 1 video link prbs test gmsl serializer downloaded from: http:///
gigabit multimedia serial link deserializer with lvds system interface max9268 26 _____________________________________________________________________________________ image-sensing applications for image-sensing applications, connect the f c to the max9268 and set cds = high for both the gmsl serial- izer and the max9268. the deserializer powers up nor- mally (sleep = 0) and continuously tries to lock to a valid serial input. table 10 summarizes both startup cases, based on the state of the gmsl serializer autos pin. case 1: autostart mode after power-up or when pwdn transitions from low to high, the gmsl serializer locks to a stable input clock and sends the high-speed data to the max9268. the deserializer locks to the serial data and outputs the video data and clock. case 2: sleep mode after power-up or when pwdn transitions from low to high, the gmsl serializer starts up in sleep mode. use the f c to wake up the serializer by sending a gmsl proto col uart frame containing at least three rising edges ( e.g., 0x66), at a bit rate no greater than 1mbps. the low -power wake-up receiver of the serializer detects the wake -up frame over the reverse control channel and powers u p. reset the sleep bit (sleep = 0) of the gmsl seriali zer using a regular control-channel write packet to pow er up the device fully. send the sleep bit write packet a t least 500 f s after the wake-up frame. the gmsl serializer goes back to sleep mode if its sleep bit is not cleared within 5ms (min) after detecting a wake-up frame. applications information error checking the max9268 checks the serial link for errors and s tores the number of detected decoding errors in the 8-bit register decerr (0x0d). if a large number of decodi ng errors are detected within a short duration, the de serializer loses lock and stops the error counter. the deseria lizer then attempts to relock to the serial data. decerr resets upon successful video link lock, successful readout of decerr (through uart), or whenever autoerror reset is enabled. the max9268 does not check for decoding er rors during the internal prbs test and decerr is reset t o 0x00. table 10. startup selection for image-sensing applications (cds = high) figure 23. max9268 state diagram, cds = high (camera application) power-on idle serial port locking all states power-down or power-off no signal detected pwdn = high, power-on config link operating video link operating video link locked video link unlocked prbsen = 0prbsen = 1 video link prbs test config link unlocked config link locked signal detected program registers pwdn = low or power-off (reverse channel active) case autos (gmsl serializer) gmsl serializer power-up state max9268 power-up state link startup mode 1 low serialization enabled normal (sleep = 0) autostart 2 high sleep mode (sleep = 1) normal (sleep = 0) gmsl serializer is in sleep mode. wake up the serializer through the control channel ( f c attached to max9268). downloaded from: http:///
gigabit multimedia serial link deserializer with lvds system interface max9268 ______________________________________________________________________________________ 27 err output the max9268 has an open-drain err output. this output asserts low whenever the number of decoding errors exceeds the error threshold errthr (0x0c) during no rmal operation, or when at least one prbs error is detec ted dur- ing the prbs test. err reasserts high whenever decerr (0x0d) resets due to decerr readout, video link loc k, or autoerror reset. autoerror reset the default method to reset errors is to read the respective error registers in the max9268 (0x0d, 0x 0e). autoerror reset clears the decoding error counter d ecerr and the err output ~1 f s after err goes low. autoerror reset is disabled on power-up. enable autoerror reset through autorst (0x06 d6). autoerror reset does not run when the device is in prbs test mode. self-prbs test the gmsl serializer/max9268 link includes a prbs pa ttern generator and bit-error verification function. set prbsen = 1 (0x04 d5) first in the gmsl serializer and then the max9268 to start the prbs test. set prbsen = 0 (0x0 4 d5) first in the max9268 and then the gmsl serializer t o exit the prbs self-test. the max9268 uses an 8-bit register (0x0e) to count the number of detected errors. the control link also controls the start and stop of the error count ing. during prbs mode, the device does not count decoding error s and the max9268 err output reflects prbs errors only. microcontrollers on both sides of the gmsl link (dual c control) usually a single f c is used for gmsl device programming and control-channel communications and is located e ither on the serializer side for video-display applicatio ns or on the deserializer (max9268) side for image-sensing a ppli- cations. in the former case, the cds pins of the se rializer/ deserializer are set to low; in the latter case, th ey are set to high. however, if the cds pin of the serializer is low and the same pin on the deserializer is high, then f cs connected at each device are enabled as masters simultaneousl y. in such a case, the f c on either side communicates with the gmsl serializer and the max9268. contention can occur if the f cs attempt to use the control channel at the same time. the serializer/deserializ er do not in themselves provide a way to avoid contention . the fact that an acknowledge is not received when conte ntion occurs can be used to trigger a retry. alternativel y, a higher layer protocol can be implemented to avoid contenti on. in addition, if uart communication across the serial l ink is not required, the f cs can disable the forward and reverse control channel through the revccen and fwdccen bits (0x04 d[1:0]) in the gmsl serializer/max9268. uart communication across the serial link is prevented a nd therefore contention between f cs can no longer occur. during dual f c operation, if one of the cds pins on either side changes state, the link resumes the correspond ing state described in the link startup procedure section. as an example of dual f c use in an image-sensing appli- cation, the gmsl serializer can be in sleep mode an d waiting for wake-up by the max9268. after wake-up, the serializer-side f c sets the gmsl serializer?s cds pin low and assumes master control of the serializer?s regi sters. changing the clock frequency both the video clock rate (f txclkout_ ) and the control- channel clock rate (f uart ) can be changed on-the-fly to support applications with multiple clock speeds. it is recommended to enable the serial link after the vid eo clock stabilizes. stop the video clock for 5 f s and restart the serial link, or toggle seren after each change in the vide o clock frequency, to recalibrate any automatic settings if a smooth frequency change cannot be guaranteed. the reverse control channel remains unavailable for 350 f s after serial link start or stop. limit on-the-fly changes in f uart to factors of less than 3.5 at a time to ensure that the devic e recog- nizes the uart sync pattern. for example, when lowe ring the uart frequency from 1mbps to 100kbps, first sen d data at 333kbps and then at 100kbps to have reducti on ratios of 3 and 3.333, respectively. lock output loopback for quick loss-of-lock notification, the max9268 ca n loop back its lock output to the gmsl serializer using t he int signal. connect the lock output to the int inpu t of the max9268. the interrupt output on the gmsl seria lizer follows the transitions at the lock output. reverse control- channel communication does not require an active fo rward link to operate and accurately tracks the lock stat us of the video link. lock asserts for video link only and no t for the configuration link. gpios the max9268 has two open-drain gpios available. gpio1out and gpio0out (0x06 d3, d1) set the output state of the gpios. the gpio input buffers are alwa ys enabled. the input states are stored in gpio1 and g pio0 (0x06 d2, d0). set gpio1out/gpio0out to 1 when using gpio1/gpio0 as an input. downloaded from: http:///
gigabit multimedia serial link deserializer with lvds system interface max9268 28 _____________________________________________________________________________________ programming the device addresses both the gmsl serializer and the max9268 have progr am- mable device addresses. this allows multiple gmsl d evic- es along with i 2 c peripherals to coexist on the same control channel. the serializer device address is stored in registers 0x00 of each device, while the deserializer device address is stored in register 0x01 of each device. to chang e the device address, first write to the device whose add ress changes (register 0x00 of the gmsl serializer for s erializer device address change, or register 0x01 of the max9 268 for deserializer device address change). then write the same address into the corresponding register on the other device (register 0x00 of the max9268 for serializer device address change, or register 0x01 of the gmsl serial izer for deserializer device address change). 3-level inputs for default device address add0 and add1 are 3-level inputs, which set the dev ice addresses stored in the max9268 (table 2). set the desired device addresses by connecting add0/add1 through a pullup resistor to iovdd, a pulldown resi stor to gnd, or to high impedance. for digital control, use three- state logic to drive the 3-level logic inputs. add0/add1 set the device addresses in the max9268 only and not the gmsl serializer. set the gmsl serial- izer?s add0/add1 inputs to the same settings as the max9268; alternatively, write to registers 0x00 and 0x01 of the gmsl serializer to reflect any changes made due to the 3-level inputs. choosing i 2 c/uart pullup resistors both i 2 c/uart open-drain lines require pullup resistors to provide a logic-high level. there are trade-offs be tween power dissipation and speed, and a compromise made in choosing pullup resistor values. every device conne cted to the bus introduces some capacitance even when th e device is not in operation. i 2 c specifies 300ns rise times to go from low to high (30% to 70%) for fast mode, whi ch is defined for data rates up to 400kbps (see the i 2 c specifica- tions in the ac electrical characteristics section for details). to meet the fast-mode rise-time requirement, choose the pullup resistors such that rise time t r = 0.85 x r pullup x c bus < 300ns. the waveforms are not recognized if the transition time becomes too slow. the max9268 suppo rts i 2 c/uart rates up to 1mbps. ac-coupling ac-coupling isolates the receiver from dc voltages up to the voltage rating of the capacitor. four capaci tors (two at the serializer output and two at the deseri alizer input) are needed for proper link operation and to provide protection if either end of the cable is shorted to a high volt- age. ac-coupling blocks low-frequency ground shifts and low-frequency common-mode noise. selection of ac-coupling capacitors voltage droop and the digital sum variation (dsv) o f transmitted symbols cause signal transitions to sta rt from different voltage levels. because the transition ti me is finite, starting the signal transition from different volta ge levels causes timing jitter. the time constant for an ac-c oupled link needs to be chosen to reduce droop and jitter to an acceptable level. the rc network for an ac-coupled link consists of the cml receiver termination resistor ( r tr ), the cml driver termination resistor (r td ), and the series ac-coupling capacitors (c). the rc time constant fo r four equal-value series capacitors is (c x (r td + r tr ))/4. r td and r tr are required to match the transmission line imped- ance (usually 100 i ). this leaves the capacitor selection to change the system time constant. use at least 0. 2 f f high-frequency surface-mount ceramic capacitors, wi th sufficient voltage rating to withstand a short to b attery, to pass the lower speed reverse control-channel signal . use capacitors with a case size less than 3.2mm x 1.6mm to have lower parasitic effects to the high-speed sign al. power-supply circuits and bypassing the max9268 uses a 3.0v to 3.6v v avdd and v dvdd . all single-ended inputs and outputs on the max9268 deri ve power from a 1.7v to 3.6v v iovdd , which scales with iovdd. proper voltage-supply bypassing is essential for high-frequency circuit stability. cables and connectors interconnect for cml typically has a differential i mpedance of 100 i . use cables and connectors that have matched differential impedance to minimize any impedance di s- continuities. twisted-pair and shielded twisted-pai r cables tend to generate less emi due to magnetic-field can celing effects. balanced cables pick up noise as common mo de rejected by the cml receiver. table 11 lists the su ggested cables and connectors used in the gmsl link. downloaded from: http:///
gigabit multimedia serial link deserializer with lvds system interface max9268 ______________________________________________________________________________________ 29 board layout separate the digital signals and cml/lvds high-spee d signals to prevent crosstalk. use a four-layer pcb with separate layers for power, ground, cml/lvds, and di gital signals. layout pcb traces close to each other for a 100 i differential characteristic impedance. the trace di mensions depend on the type of trace used (microstrip or str ipline). note that two 50 i pcb traces do not have 100 i differen- tial impedance when brought close together because the impedance goes down when the traces are brought clo ser. route the pcb traces for a cml/lvds channel (there are two conductors per cml/lvds channel) in paralle l to maintain the differential characteristic impedance. avoid vias. keep pcb traces that make up a differential p air equal length to avoid skew within the differential pair. esd protection the max9268 esd tolerance is rated for human body model, iec 61000-4-2, and iso 10605. the iso 10605 and iec 61000-4-2 standards specify esd tolerance f or electronic systems. cml/lvds i/o are tested for iso 10605 esd protection and iec 61000-4-2 esd protection. al l pins are tested for the human body model. the human body model discharge components are c s = 100pf and r d = 1.5k i (figure 24). the iec 61000-4-2 discharge components are c s = 150pf and r d = 330 i (figure 25). the iso 10605 discharge components are c s = 330pf and r d = 2k i (figure 26). table 11. suggested connectors and cables for gmsl figure 24. human body model esd test circuit figure 26. iso 10605 contact discharge esd test circuit figure 25. iec 61000-4-2 contact discharge esd test circuit vendor connector cable jae electronics, inc. mx38-ff a-bw-lxxxxx nissei electric co., ltd. gt11l-2s f-2wme awg28 rosenberger hochfrequenztechnik gmbh d4s10a-40ml5-z dacar 538 storagecapacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance 1m i r d 1.5k i c s 100pf storagecapacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance r d 2k i c s 330pf c s 150pf storagecapacitor high- voltage dc source device under test charge-current- limit resistor discharge resistance r d 330 i downloaded from: http:///
gigabit multimedia serial link deserializer with lvds system interface max9268 30 _____________________________________________________________________________________ table 12. register table (see table 1) register address bits name value function default value 0x00 d[7:1] serid xxxxxxx serializer device address. power-up default address determined by add0 and add1 (see table 2). xx00xx0 d0 ? 0 reserved 0 0x01 d[7:1] desid xxxxxxx deserializer device address. power-up default address determined by add0 and add1 (see table 2). xx01xx0 d0 ? 0 reserved 0 0x02 d[7:6] ss 00 no spread spectrum. power-up default when ssen = low. 00, 01 01 q 2% spread spectrum. power-up default when ssen = high. 10 no spread spectrum 11 q 4% spread spectrum d5 ? 0 reserved 0 d4 audioen 0 disable i 2 s channel 1 1 enable i 2 s channel d[3:2] prng 00 12.5mhz to 25mhz pixel clock 11 01 25mhz to 50mhz pixel clock 10 50mhz to 104mhz pixel clock 11 automatically detect the pixel clock range d[1:0] srng 00 0.5gbps to 1gbps serial-data rate 11 01 1gbps to 2gbps serial-data rate 10 2gbps to 3.125gbps serial-data rate 11 automatically detect serial-data rate 0x03 d[7:6] autofm 00 calibrate spread-modulation rate only once after locking 00 01 calibrate spread-modulation rate every 2ms after locking 10 calibrate spread-modulation rate every 16ms after locking 11 calibrate spread-modulation rate every 256ms after locking d5 ? 0 reserved 0 d[4:0] sdiv 00000 autocalibrate sawtooth divider 00000 xxxxx manual sdiv setting. see the manual programming of spread-spectrum divider section. downloaded from: http:///
gigabit multimedia serial link deserializer with lvds system interface max9268 ______________________________________________________________________________________ 31 table 12. register table (see table 1) (continued) register address bits name value function default value 0x04 d7 locked 0 lock output is low 0 (read only) 1 lock output is high d6 outenb 0 enable outputs 0 1 disable outputs d5 prbsen 0 disable prbs test 0 1 enable prbs test d4 sleep 0 normal mode. default value depends on cds and ms pin values at power-up). 0, 1 1 activate sleep mode. default value depends on cds and ms pin values at power-up). d[3:2] inttype 00 base mode uses i 2 c peripheral interface 00 01 base mode uses uart peripheral interface 10, 11 base mode peripheral interface disabled d1 revccen 0 disable reverse control channel to serializer (sending) 1 1 enable reverse control channel to serializer (sending) d0 fwdccen 0 disable forward control channel from serializer (receiving) 1 1 enable forward control channel from serializer (receiving) 0x05 d7 i2cmethod 0 i 2 c conversion sends the register address 0 1 disable sending of i 2 c register address (command- byte-only mode) d[6:5] hpftune 00 7.5mhz equalizer highpass cutoff frequency 01 01 3.75mhz cutoff frequency 10 2.5mhz cutoff frequency 11 1.87mhz cutoff frequency d4 pdhf 0 high-frequency boosting enabled 0 1 high-frequency boosting disabled d[3:0] eqtune 0000 2.1db equalizer boost gain 0100, 1001 0001 2.8db equalizer boost gain 0010 3.4db equalizer boost gain 0011 4.2db equalizer boost gain 0100 5.2db equalizer boost gain. power-up default when eqs = high. 0101 6.2db equalizer boost gain 0110 7db equalizer boost gain 0111 8.2db equalizer boost gain 1000 9.4db equalizer boost gain 1001 10.7db equalizer boost gain. power-up default when eqs = low. 1010 11.7db equalizer boost gain 1011 13db equalizer boost gain 11xx do not use downloaded from: http:///
gigabit multimedia serial link deserializer with lvds system interface max9268 32 _____________________________________________________________________________________ table 12. register table (see table 1) (continued) register address bits name value function default value 0x06 d7 ? 0 reserved 0 d6 autorst 0 do not automatically reset error registers and outputs 0 1 automatically reset error registers and outputs d5 disint 0 enable interrupt transmission to serializer 0 1 disable interrupt transmission to serializer d4 int 0 int input = low (read only) 0 (read only) 1 int input = high (read only) d3 gpio1out 0 output low to gpio1 1 1 output high to gpio1 d2 gpio1 0 gpio1 is low 1 (read only) 1 gpio1 is high d1 gpio0out 0 output low to gpio0 1 1 output high to gpio0 d0 gpio0 0 gpio0 is low 1 (read only) 1 gpio0 is high 0x07 d[7:0] ? 01010100 reserved 01010100 0x08 d[7:0] ? 00110000 reserved 00110000 0x09 d[7:0] ? 11001000 reserved 11001000 0x0a d[7:0] ? 00010010 reserved 00010010 0x0b d[7:0] ? 00100000 reserved 00100000 0x0c d[7:0] errthr xxxxxxxx error threshold for decoding errors. err = low when decerr > errthr. 00000000 0x0d d[7:0] decerr xxxxxxxx decoding error counter. this counter remains zero while the device is in prbs test mode. 00000000 (read only) 0x0e d[7:0] prbserr xxxxxxxx prbs error counter 00000000 (read only) 0x12 d7 mclksrc 0 mclk derived from pclk (see table 5) 0 1 mclk derived from internal oscillator d[6:0] mclkdiv 0000000 mclk disabled 0000000 xxxxxxx mclk divider 0x13 d[7:5] ? xxx reserved (read only) d[4:0] ? 10000 reserved 10000 downloaded from: http:///
gigabit multimedia serial link deserializer with lvds system interface max9268 ______________________________________________________________________________________ 33 table 12. register table (see table 1) (continued) x = don?t care. register address bits name value function default value 0x14 d[7:6] ? 00 reserved 00 d5 forcelvds 0 normal operation 0 1 force lvds outputs low d4 dcs 0 normal driver current for cmos outputs (ws, sck, sd/ cntl0, cntl1, cntl2/mclk) 0 1 strong driver current for cmos outputs (ws, sck, sd/ cntl0, cntl1, cntl2/mclk) d3 discntl1 0 serial-data bit 27 is mapped to cntl1 0 1 cntl1 forced low d2 disres 0 serial-data bit 27 is mapped to res 0 1 res bit forced low d[1:0] ilvds 00 1.75ma lvds current 01 01 3.5ma lvds current 10 do not use 11 7ma lvds current 0x1e d[7:0] id 00000100 device identifier (max9268 = 0x04) 00000100 (read only) 0x1f d[7:5] ? 000 reserved 000 (read only) d4 caps 0 not hdcp capable 0 (read only) 1 hdcp capable d[3:0] revision xxxx device revision (read only) downloaded from: http:///
gigabit multimedia serial link deserializer with lvds system interface max9268 34 _____________________________________________________________________________________ package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a ?+?, ?#?, or ?-? in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. chip information process: cmos typical application circuit ws lflt intms sck sd tx rx tclkout+/- txout0+/- to txout2+/- cds int rx/sda tx/scl lock ws sck sd/cntl0 sd sck ws sda scl cdsautos rx/sda in+in- in to peripherals display display application note: not all pullup/pulldown resistors are shown. see pin description for details. rx0+/-to rx2+/- rxclk+/- out pll out+ 45k i 45k i 5k i 5k i 50k i 50k i lmn1lmn0 out- tx/scllflt int ms ws sck sd/cntl0 txclk+/- rxclkin+/- rxin0+/-to rxin2+/- tx0+/- to tx2+/- gpu ecu mclk uartaudio max9249 max9268 max9850 package type package code outline no. land pattern no. 48 tqfp-ep c48e+8 21-0065 90-0138 downloaded from: http:///
gigabit multimedia serial link deserializer with lvds system interface max9268 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 35 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 4/10 initial release ? 1 5/10 changed conditions for lvds output enable/disable times and sck jitter limits in the ac electrical characteristics table 5 2 1/11 added patent pending to features 1 downloaded from: http:///

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